High-Performance and Area-Efficient VLSI Architecture for Secure Data Encryption Using AES Algorithm

Abstract

In today’s rapidly evolving digital ecosystem, the protection of sensitive data has become a critical requirement for applications such as cloud computing, Internet of Things (IoT), embedded systems, and secure communication networks. The Advanced Encryption Standard (AES) is widely adopted due to its strong security and standardization; however, software-based AES implementations often suffer from high latency, limited throughput, and increased power consumption, making them unsuitable for real-time and resource-constrained environments. This work presents a high-performance and area-efficient VLSI architecture for AES-128 encryption, specifically optimized for FPGA-based platforms. The proposed design is implemented using Verilog HDL and realized on a Xilinx Spartan-6 FPGA. A sequential, round-based architecture is employed to achieve an optimal balance between performance, area utilization, and power efficiency. To reduce hardware overhead, a memory-based S-Box implementation using Block RAM is adopted, significantly minimizing logic duplication and resource consumption. Core AES transformations—SubBytes, ShiftRows, MixColumns, AddRoundKey, and Key Expansion—are modularly designed and controlled using a finite state machine (FSM). Functional correctness is validated using standard AES test vectors, while synthesis and timing analysis are carried out using Xilinx ISE and Cadence Genus. The results confirm that the proposed architecture is well-suited for real-time encryption in embedded and low-power systems. By offering a balance between performance and resource efficiency, the proposed AES architecture lays a strong foundation for future research and development in secure VLSI systems.

Keywords: cryptography, VLSI, FPGA, AES, AES-128, Hardware Encryption, Verilog HDL Low Power, s-box optimization.