Somu Goudagavi

https://doi.org/10.64823/ijter.2601001

This work presents a fault-tolerant dual-port RAM architecture implemented on an FPGA, aimed at improving memory reliability under concurrent access conditions. The proposed design integrates error correction coding (ECC) to detect and correct memory errors during read operations. A round-robin arbitration scheme is employed to handle simultaneous write conflicts between two independent ports accessing the same memory address. The memory is organized using even and odd banks to improve access efficiency and simplify arbitration. Fault injection is incorporated at the memory level to emulate single-bit and double-bit errors, enabling validation of error detection and correction functionality. An automatic scrubbing mechanism updates corrected data back into memory to prevent error accumulation. The design is described in Verilog, simulated for functional verification, and implemented on a Spartan-6 FPGA using Xilinx ISE 14.7. Simulation results and hardware outputs confirm correct dual-port operation, arbitration behavior, and reliable data access. Resource utilization and timing analysis demonstrate that fault tolerance is achieved with acceptable hardware overhead, making the architecture suitable for reliable FPGA-based memory systems.